Semiconductor technology and chip manufacturing advances have resulted in a steady increase of on-chip clock frequencies, the number of transistors on a single chip and the die size itself, coupled with a corresponding decrease in chip supply voltage and chip feature size. Generally, all other factors being constant, the power consumed by a given clocked unit increases linearly with the frequency of switching within it. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, net power consumption reduction is important but, without degrading performance below acceptable levels.
To minimize power consumption, most integrated circuits (lCs) used in such low end systems (and elsewhere) are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (ideally modeled as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa.
For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, the PFET pulling the output high and the NFET pulling the output low at opposite input signal states. Ideally, when the gate of a NFET is below some positive threshold voltage (Vt) with respect to its source, the NFET is off, i.e., an open switch. Above Vt, the NFET is on conducting current, i.e., the switch is closed. Similarly, a PFET is off when its gate is above its Vt, i.e., less negative, and on below Vt. Thus, ideally, the CMOS inverter in particular and CMOS circuits in general pass no static (DC) current. Therefore, ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
Some applications, such as logic circuits for general and special purpose processors, require a High Performance (HP) FET that is capable of fast transitions. In other applications, power consumption is of concern, especially for portable electronic devices that operate with battery power. For such applications, FET leakage can become a substantial source of power consumption, even when such a device is in a standby state. In these situations a Low Leakage (LL) FET is desirable.
Modern electronic devices may include instances where a combination of High Performance (HP) FETs and Low Leakage (LL) FETs are necessary. Therefore, it is desirable to have an improved structure and method for fabricating a combination of HP FETs and LL FETs on a single integrated circuit (IC).